Special Topic on Steep Slope Transistors for Energy-Efficient Computing & More
Special Topic on Steep Slope Transistors for Energy-Efficient Computing & More
Guest Editor:
Alan Seabaugh, University of Notre Dame, seabaugh.1@nd.edu
Editor-in-Chief:
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu
Aims and Scope:
Tunnel field-effect transistors (FETs) and low-subthreshold-swing steep-slope (SS) transistors hold promise to outperform complementary metal-oxide semiconductor technology (CMOS) at low voltage and realize more energy-efficient logic for computation. The aim of this special topics issue is to highlight experimental advances and ideas that make SS transistors attractive for integration with CMOS to realize better power-performance logic. Aspirational characteristics for n- and p-type steep transistors can be summarized as follows: drain currents exceeding 200 mA/mm at a supply voltage below 0.4 V, with SS less than 60 mV/decade beginning near 1 mA/mm and spanning more than 4 decades. Papers describing theory and modeling of transistors which can meet and surpass these goals are of interest, as are papers which assess the full design stack from devices to circuits and architecture to applications to identify system bottlenecks and inform technology development for computing, communications, or other applications. Materials approaches are not restricted to silicon CMOS and can be based on any semiconductor technology and incorporate multiferroic or other performance boosters. New approaches based on three-dimensional integration, heterogeneous integration, processing, or insights from manufacturing are also within the scope of this issue to advance understanding and progress in SS transistors.
Topics of Interest:
TFET and other steep slope transistors with path to outperform CMOS at low voltage
• Experimental progress
• Theory and modeling
• Si, III-V, III-N, two-dimensional semiconductors and heterojunctions
• Multiferroic and other material/device design approaches
• 3-D integration, heterogeneous integration, processing, manufacturing
Full-stack design to inform technology development
Important Dates:
· Open for Submission: June 1st, 2023
· Submission Deadline: Sept. 1st, 2023 EXTENDED: Sept. 29th, 2023
· First Notification: Oct. 1st, 2023
· Revision Submission: Oct. 15th, 2023
· Final Decision: Nov. 15th, 2023
Online Special Topic Publication: Dec. 1st, 2023
Submit your article through the JxCDC IEEE Author Portal:
https://ieee.atyponrex.com/journal/JXCDC
JxCDC is an Open Access only Publication:
Article Processing Charge (APC): US $1950
For papers submitted in 2023, the APC is US $1950 plus applicable local taxes.
The following discounts apply:
- IEEE Members receive a 5% discount.
- IEEE Society Members receive a 20% discount.
Discounts do not apply to undergraduate and graduate students. These discounts cannot be combined.
Paper submissions must be done through the IEEE Authro Portal website: https://ieee.atyponrex.com/journal/JXCDC
Guidelines for papers and supplementary materials, as well as a paper template, are provided at this website.