Follow: Share:Share


Anantha P. Chandrakasan Wins 2013 IEEE Donald O. Pederson Award
ISSCC Conference Chair To Be Feted during ISSCC 2013 Plenary Awards Program

pdrsnmedal1anantha ieee photoOn Monday morning February 18, ISSCC Conference Chair Anantha P. Chandrakasan will be called to the podium, in an uncommon reversal of roles, to be presented with the 2013 Donald O. Pederson Award for “pioneering techniques in low-power digital and analog CMOS design.” 

MIT colleague, Dennis Buss, recalls the scene at ISSCC in 1994 when Anantha presented the results of his PhD research.


Revolutionary Doctoral Thesis Shocks the Industry 

“Future terminals will allow users untethered access to multi-media information servers that are interconnected through high-bandwidth network backbones.  This paper describes a chipset (six chips) for such a terminal……  The chips provide protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion at power consumption less that 5 mW.”

This is the opening of the ISSCC paper in February 1994 that described Anantha’s thesis research. 

It is not surprising that the conference hall in the San Francisco Marriott was packed when Anantha made his presentation. And for the first -- and only -- time in the history of the conference, the program committee requested that Anantha present his paper twice.  It is not surprising that the paper was selected as one of the highlights of signal processing at the 50th anniversary of the ISSCC Digest.  And it is not surprising that the JSSC paper that described these innovations in detail received the second highest number of citations in the history of the journal.

Anantha’s work introduced the concept of voltage scaling -- energy per operation is proportional to voltage squared -- as well as design techniques that allowed the minimization of power and energy required to perform a given computation. In addition,

  • It introduced the concept of parallelism to compensate for the reduction in clock rate at low voltage
  • It acknowledged the importance of algorithms that enable parallelism.  
  • It presented the importance of transistor sizing on power minimization.

At a time when switching speed and the silicon area of digital CMOS circuits were the primary design metrics used for circuit optimization and comparable chips operated at 100X higher power, 5 mW for six chips was a revolutionary finding. It shocked the industry.

Today, Anantha’s visionary concepts provide the core ideas for ultra-low power design for remote sensor and medical monitoring  applications.


A full-length profile of Anantha, with commentary by Mark Horowi tz, his Pederson nominator, and ISSCC colleagues, Laura Fujino and Ken Smith, will appear in the winter 2013 SSCS Magazine.

Compiled by K. Olstein